The present invention relates to processors with microcoded instruction sets and, more particularly, to instruction sets which provide for processor operations in which not all the bits of an instruction word are required.
In the organization of a typical computer processor, as shown in FIG. 1, the instructions which are to be executed are stored in a memory block 10. In such an organization, the instruction signals address the locations in a ROM which contains microinstruction signals which are the basis for the control signals in the processor. Thus the processor has a ROM-address register block 17 as shown in FIG. 1. A micro-address register 13 holds the address of a memory location in the ROM 15. The register 13 is connected to the output terminals of a multiplexer 12, which selects address signals from an instruction register block 11 and an incrementor 14. The incrementor 14 increments the address held in the register 13 for sequential addressing of the microinstructions in the ROM.
Fed by the memory block 10, the instruction register block 11 holds instructions which are to be executed or immediate data (or address) and control signals which are to be sent directly to a control decode block 16. The control decode block 16 receives the microinstruction signals from the ROM 15 or direct signals from the instruction register block 11 to generate and time the control signals for the processor.
However, most processors have sets of instructions of varying length and not all the bits in an instruction word are required for an operation. For example, in instruction sets having one-byte instructions with instruction words of two or more bytes, the second byte in the instruction word may not be needed for the execution of the first byte. This implies that much of the address space of the ROM 15 is wasted because the second byte of the instruction word in the register 13 is not required to address the selected microinstruction.
In many systems, as in computer mainframes, the waste of ROM space is not significant. However, in microprocessors the contrary may be true. Such a ROM can occupy a significant fraction of the surface area of the microprocessor semiconductor chip. A reduction in size of the ROM, and hence the overall chip, is desirable for various reasons. A smaller chip decreases the chances of defects in an individual chip during the manufacturing process. Costs are lowered. The units in the microprocessor are packed closer in a smaller chip and operating speeds are increased. Finally, the smaller chip follows the trend in microprocessor-based technology. Increased miniaturization results in lighter, smaller and more convenient computers.
The present invention is thus directed towards a more efficient implementation of an instruction set in which not all the bits in an instruction word are required to carry out an operation.